The AMC-ADIO24 is equipped with a Spartan FPGA that manages the I/O data exchange in cooperation with the PCIe bridge. FIFOs for input and output direction and DMA to the PCIe host PCUs memory minimizes undesired latency during PCIe read cycles at higher data rates. Read cycles of the PCIe CPU are reduced to setup and diagnosis tasks
The eight over voltage protected analog inputs are connected to eight 16 bit A/D converters with a sampling rate of up to 200 kHz each
Boht 16 bit analog outputs have a differential and a single ended output circuit, accessible at separate pins at a Harting har-link connector. The outputs are transient and short circuit protected.
Each of the 24 TTL-level I/Os can be separately configured as input or output. The outputs can be configured as high side driver, low side driver or both (sink/source). The I/O port`s state can be read back in any configuration via a comparator with hysteresis.
The firmware offers a so called "Timing-Routing-Pool" with various trigger conditions (RS-485 trigger input, timer, software, free flow) that can be individually evaluated for each I/O.
For setup and I/O data exchange a comprehensive register description is available.